Drive Strength and LVCMOS Based Dynamic Power Reduction of ALU on FPGA
2013-05-06 13:59:22   来源：   评论：0 点击：

Abstract— In this paper, we achieve 35.9% dynamic power reduction and 36.11% dynamic current reduction by shfting drive strength from 24mA to 2mA on LVCMOS25 when 2.5 V is output driver supply voltage. and 1.0V is
input supply voltage. we achieve 30% dynamic power reduction and 21.7% dynamic current reduction by shfting drive strength from 24mA to 2mA on LVCMOS12 when 1.2V is output driver supply voltage. and 1.0V is input supply voltage. Virtex-6 XC6VLX75TFF484-1 FPGA device family is used to verify drive strength based dynamic power and current reduction. The ALU designed using Verilog HDL coding, implemented using Xilinx Integrated Software Environment (ISE) and validated using iSim, XPower, iMPACT and ChipScope. Dynamic power and dynamic current both are directly proportional to drive strength is our another observation. In view of power consumption, DCI is highest power consumer in between all used IO Standard in virtex-6 FPGA and LVCMOS is the best IO standard in term of power consumption. 

Index Terms—Dynamic Power Reduction, Low Voltage, Dynamic Current Reduction, Drive Strength, IOStandard, Pull Type, Input Supply Voltage

Cite: Bishwajeet Pandey, Mayank Kumar, Nirmal Roberts, and Manisha Pattanaik, "Drive Strength and LVCMOS Based Dynamic Power Reduction of ALU on FPGA," Lecture Notes on Information Theory, Vol.1, No.1, pp. 60-63, March 2013. doi: 10.12720/lnit.1.1.60-63